Delivery: Can be download immediately after purchasing. For new customer, we need process for verification from 30 mins to 12 hours.
Version: PDF/EPUB. If you need EPUB and MOBI Version, please contact us.
Compatible Devices: Can be read on any devices.
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
This is a digital product.
Fault-Tolerance Techniques for SRAM-Based FPGAs is written by Fernanda Lima Kastensmidt; Ricardo Reis and published by Springer. The Digital and eTextbook ISBNs for Fault-Tolerance Techniques for SRAM-Based FPGAs are 9780387310695, 038731069X and the print ISBNs are 9781441940520, 1441940529. Additional ISBNs for this eTextbook include 9780387310688.

Piano for the Developing Musician, Media Update eBook
Taking Charge of Your Fertility eBook
Geometric Dimensioning and Tolerancing eBook
Limnology: Lake and River Ecosystems eBook
Financial Accounting, Enhanced eText eBook
McGraw-Hill Education TEAS Review, Second Edition eBook
Aquaculture Landscapes: Fish Farms and the Public Realm eBook
The Young Entrepreneur's Guide to Starting and Running a Business eBook
Pearson Reviews & Rationales: Medical-Surgical Nursing with Nursing Reviews & Rationales, 4th Edition eBook
Terrorism and Homeland Security eBook
What to Think About Machines That Think: Today's Leading Thinkers on the Age of Machine Intelligence eBook
Automotive Technology: A Systems Approach, 7th Edition eBook
Ace the TOEFL Essay (TWE): Everything You Need for the Test of Written English eBook
Cracking the AP Chemistry Exam 2019, Premium Edition eBook
The Foundations of Mathematics eBook
Architecture in Formation eBook
Being Salmon, Being Human: Encountering the Wild in Us and Us in the Wild eBook
Nutrition, Health, and Safety for Young Children: Promoting Wellness, 4th Edition eBook
Trends and Applications in Knowledge Discovery and Data Mining PAKDD 2015 Workshops: BigPMA, VLSP, QIMIE, DAEBH, Ho Chi Minh City, Vietnam, May 19-21, 2015. Revised Selected Papers eBook
Design Thinking: Understanding How Designers Think and Work eBook
Introduction to e-Supply Chain Management: Engaging Technology to Build Market-Winning Business Partnerships eBook
Network Security Essentials eBook 


Reviews
There are no reviews yet.