ASIC and FPGA Verification: A Guide to Component Modeling eBook

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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs.

ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.

*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model “off-the-shelf” or “IP” digital components for use in FPGA and board-level design verification.

This is a digital product.

ASIC and FPGA Verification: A Guide to Component Modeling is written by Munden, Richard and published by Morgan Kaufmann. The Digital and eTextbook ISBNs for ASIC and FPGA Verification: A Guide to Component Modeling are 9780125105811, 9780080475929, 0080475922 and the print ISBNs are 9780125105811, 0125105819.